The present invention relates to the field of microelectronic circuit fabrication, more particularly to fabrication of flash memory microelectronic circuits, and even more particularly to a method for fabrication of an intermediate device containing a low resistance common source line for fabrication of flash memory microelectronic circuits.
High performance NOR-type flash memories require high density and high operating speed as the device dimensions are scaled down. A low resistance common source line for cells in different bit-lines, but on the same word-line, is used in flash memory devices to reduce memory core cell size and to improve circuit density.
Prior art advanced flash memory technology in which shallow trench isolation (STI) method is used in fabrication of memory core cells, requires a series of steps prior to fabrication of the low resistance common source line, including the steps of 1) forming shallow trenches in the chip substrate, 2) filling the shallow trenches with field oxide, 3) applying an SAS etch mask, 4) using SAS etch to remove field oxide fill from unprotected STI regions, 5) removing the damaged SAS etch mask, 6) applying a high energy ion implant mask, 7) forming a low resistance common source line by applying a high energy ion implant(Vss Core Implant (VCI), to the unprotected regions, 8) removing the VCI mask, and 9) filling the STI regions with field oxide. The remainder of the flash memory microelectronic circuitry, such as source and drain regions and gate structures are then conventionally formed.
The prior art method requires an SAS etch process be used to remove field oxide from the STI regions prior to formation of the low resistance common source line. SAS etch is an aggressive process, using a strong oxide etch that can damage tunnel oxide corners, oxide-nitride-oxide (ONO) layers, and the SAS etch mask, requiring replacement of the SAS mask before applying a new mask for VCI implant mask and forming the low resistance common source line. The SAS process is a multistep process which is inefficient and produces damage resulting in reduced wafer yield and reduced microchip reliability. What is needed is a simplified method for forming a higher quality low resistance common source line microelectronic structure, thereby increasing production efficiency by reducing fabrication steps and by reducing damage to gate structures, providing a higher production yield and cell reliability.
Specific details of the invention are included in the modes for carrying out the invention section and as described in the drawings and as claimed.
The present invention is a simplified method for forming an improved microelectronic component having a low resistance common source line for all devices on a different bit line and the same word-line of high performance NOR-type flash memory microelectronic circuits. For advanced flash memory technology where STI method is to be used in fabrication of flash memory core cells, the method of the present invention completely eliminates the use of SAS etch process, and, alternatively, uses only VCI mask and implant steps to produce a high energy ion implant to form a low resistance common source line for all cells on a different bit line and the same word-line. The method of the present invention eliminates the steps of 1) filling the shallow trenches with field oxide, 2) applying an SAS etch mask, 3) using SAS etch to remove field oxide fill from unprotected STI regions, and removing the damaged SAS etch mask. In the present invention, the VCI implant is performed after formation of shallow trenches and eliminates the need for field oxide fill, thus there is no need to use SAS etch since the low resistance common source line is formed prior to STI field oxide fill. The present invention method consists of the steps of 1) forming shallow trenches in the substrate, 2) applying a VCI mask, 3) applying a VCI implant thereby forming the low resistance common source line, 4) removing the VCI mask, 5) forming a liner oxide layer, and filling the shallow trench region with field oxide. The memory structure is then conventionally formed as is known in the art. Elimination of the SAS etch associated steps creates a simplified fabrication method resulting in more efficient fabrication. Further, elimination of the SAS etch associated steps avoids damage to the device surface by the SAS etch, resulting in higher fabrication yield. The present invention is useful for ever smaller cell sizes, in which fabrication using SAS etch becomes nearly impossible.